1. Field of the Invention
The present invention relates to a data output circuit and, more particularly, to a data output circuit suitable for a semiconductor memory or similar integrated circuit operable at a high bit rate and having a plurality of bits of outputs.
2. Description of the Prior Art
Generally, an integrated circuit operable at a high bit rate has a data output circuit including, for example, a latch circuit for latching 1-bit data which are complementary to each other. In this type of data output circuit, complementary outputs of the latch circuit are routed through buffers to a pair of output transistors, e.g., n-channel metal oxide semiconductor field effect transistors (MOSFET) connected in series between two reference power sources. Output data appear on the node of such a serial connection. The latch circuit includes two NAND gates connected crosswise. It is a common practice to assign a data output circuit having this configuration to each of a plurality of bits of outputs of an integrated circuit.
In operation, complementary data to be outputted are latched by the latch circuit and fed to the pair of output transistors via the inverters to drive the transistors. As a result, the pair of output transistors are rendered conductive and nonconductive in a complementary fashion, so that a current flows from conductive one of the transistors to a load.
The above-described conventional data output circuit including a serial connection of a pair of output transistors has a noise problem. Specifically, noise is generated in the circuit when, at the final stage of operation, one of the output transistors is turned on and the other transistor is turned off to output one bit of data having a certain logical state, i.e., when a current flows from the load to one reference power source via one output transistor and a current flows from the other reference power source to the load via the other output transistor. This kind of noise is not negligible in among others, an integrated circuit having a great number of parallel bits of outputs since the number of data output circuits increases with the increase in the number of bits. The total noise of this kind is sometimes great enough to cause other circuit elements packed in the same chip to malfunction and is apt to increase the access time.